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TSMC to Continue Using Micro-Bump Technology for HBM Packaging
TSMC has announced that it will temporarily stick with traditional micro-bump technology for connecting high-bandwidth memory (HBM) with AI accelerators in advanced packaging. This decision, effective from September 2, comes as the company assesses the development cycle of related materials, with finer pitch micro-bumps expected to be implemented in the later stages of HBM4 and early stages of HBM5.
The current bump height for the third-generation extended HBM, known as HBM3E, ranges from 15 to 25 micrometers, while HBM4 is anticipated to be around 10 micrometers. TSMC has requested its materials and equipment partners to develop bonding and underfill solutions for approximately 5-micron bumps, with suppliers from South Korea and Japan already beginning this development. Mass production of these 5μm bumps is projected to start in the second half of 2028.
The shift towards smaller bumps is driven by the need for higher interconnection density and the height limitations of HBM cubes. JEDEC has set the maximum height for HBM stacks at 775 micrometers. In TSMC's advanced CoWoS packaging, HBM stacks are mounted onto silicon interposers via micro-bumps, with contributions from GPU and memory suppliers like SK hynix and Samsung Electronics. While hybrid bonding offers advantages for thinner and denser interconnections, TSMC continues to utilize micro-bumps for HBM connections.
Source: KLEA News